1. Field of the Invention
The present invention generally relates to controlling threshold voltage (Vth) for replacement metal gate (RMG) transistors. More specifically, a work function metal (WFM), such as TiC(Al), is inserted in NMOS and PMOS regions and then selectively oxidized to control Vth for different threshold voltages.
2. Description of the Related Art
Metal-oxide-semiconductor (MOS) transistors have typically utilized polysilicon gate electrodes due to its thermal resistive properties, since polysilicon can better withstand subsequent high temperature processing. This high temperature processing characteristic allowed polysilicon to be annealed at high temperatures along with source and drain regions. Additionally, polysilicon can advantageously block ion implantation of doped atoms into a channel region, and, due to this ion implantation blocking potential, the polysilicon allows for easy formation of self-aligned source and drain structures after gate patterning is completed.
However, polysilicon gate electrodes have higher resistivities than most metal materials. Therefore, polysilicon gate electrodes may operate at much slower speeds than gates made of metallic materials. To partially compensate for this higher resistance, polysilicon materials have been subjected to extensive and expensive silicide processing in order to increase their speed of operation to acceptable levels.
Recently, metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion, and reducing processing temperatures subsequent to metal gate formation. In the replacement metal gate process flow, a dummy gate, such as polysilicon, is removed by dry/wet etching, followed by metal deposition. In this approach, a dummy gate is formed on a semiconductor wafer through using standard polysilicon gate CMOS process flow, wherein source and drain regions are first formed using an initial gate structure used for alignment of the source/drain implantation, and the gate structure is then replaced by metal.
For example, a dielectric layer and polysilicon layer are deposited on the semiconductor substrate, which are then patterned to form the dummy gate, and gate sidewall structures are formed for the dummy gate. Source/drain regions are then formed on the semiconductor using conventional implantation processes. An insulator layer is then deposited about the dummy gate. The insulator layer is then polished to expose the polysilicon layer of dummy gate. The dummy gate is then removed by reactive ion etching (RIE) and/or wet chemical etching to form a trench in the insulator layer, and a metal is then deposited within the trench to form the metal gate.
In general, dual metal gate complementary metal oxide semiconductor (CMOS) integration schemes employ two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. In CMOS devices having a silicon channel, a conductive material having a work function of 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs, or “NFETs”) and another conductive material having a work function of 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs, or “PFETs”).
In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address these needs. In CMOS devices employing high-k gate dielectric materials, two types of gate stacks comprising suitable materials satisfying the work function requirements are needed for the PFETs and for the NFETS, in which the gate stack for the PFETs provides a flat band voltage closer to the valence band edge of the material of the channel of the PFETs, and the gate stack for the NFETs provides a flat band voltage closer to the conduction band edge of the material of the channel of the NFETs. In other words, threshold voltages need to be optimized differently between the PFETs and the NFETs.
Thus, the manufacture of dual metal gate CMOS structures is difficult because two types of metal gate electrodes are needed to provide different work functions. Integration of dual gate CMOS structures with a replacement gate structure is even more difficult because of the difficulty in patterning different metal layers in replacement gate geometries.
Moreover, it is difficult to control threshold voltage Vth for replacement metal gate (RMG) transistors. Formation of different metal gate electrodes for different polarity (e.g., PMOS/NMOS) and different threshold voltages results in high cost because the fabrication process is complex. Additionally, such complexity causes low yield because of damage on the gate dielectric during device fabrication.